In recent years, display devices in which a semiconductor thin film is formed on an insulator such as a glass substrate, in particular active matrix display devices using thin film transistors (hereinafter referred to as TFTs), have been in widespread use in various fields. An active matrix display device using TFTs has several hundred thousand to several million pixels arranged in matrix, and it displays images by controlling the electric charge in each pixel by using a TFT disposed in each pixel.
As a recent technology, the technology relating to poly-silicon TFTs in which a driver circuit is simultaneously formed in a peripheral region of a pixel portion in addition to TFTs which constitute pixels, has been developed. This technology contributes greatly to reducing devices in size and electric power consumption. Display devices have thus become indispensable devices to be used for display portions of mobile information terminals and the like, application fields of which are expanding at remarkable speed.
As the driver circuit of the display device, a CMOS circuit in which an N-channel TFT and a P-channel TFT are combined is usually adopted. The CMOS circuit has advantages in that, it can suppress the consumed current in the whole circuit and perform high speed driving since a current flows only at an instant when logic is changed and a current does not flow during a period in which a certain logic is held (as there is only a minute leak current in practice).
As mobile electronic devices are reduced in size and weight, demand for a display device using a self-light emitting element and a liquid crystal element and the like such as an organic EL element, an FED (Field Emission Display), and an element used for a liquid crystal display is rapidly increasing; however, from the viewpoint of the yield and the like, it is difficult to reduce the manufacturing cost to the level sufficiently low since the great many number of TFTs are required. It is easily supposed that the demand is further rapidly increased in future, and therefore, it is desired that the display device can be supplied more inexpensively.
As a method of fabricating a driver circuit on an insulator, there is a common method in which patterns of active layers, wirings and the like are formed through exposure treatment and etching with a plurality of photomasks. Since the number of manufacturing steps is a dominant factor in determining the manufacturing cost, a manufacturing method using as small number of manufacturing steps as possible is ideal for manufacturing driver circuits. Thereupon, a driver circuit, which is conventionally configured by the CMOS circuit, is configured by using TFTs which have either N-channel type or P-channel type conductivity. With this method, a part of an ion doping step can be omitted, and the number of the photomasks can also be reduced. Therefore, the cost reduction is achieved.
FIG. 9A shows an example of a TFT load-type inverter circuit formed by using TFTs having only one conductivity. The operation thereof is described below.
FIG. 9B shows the waveform of a signal input to the inverter circuit. The input signal amplitude is between a high potential side power supply VDD and a low potential side power supply GND. It is assumed that GND=0 V for simplicity.
The circuit operation is described now. To describe the operation simply and explicitly, the threshold voltages of N-channel type TFT which configure the circuit have no variations and represented by (VthN) across the board, and the threshold voltages of P-channel type TFTs are similarly represented by a constant value (VthP).
When a signal as shown in FIG. 9B is input to the inverter circuit and the input signal is an L signal (low potential side power supply GND), an N-channel type TFT 904 is turned OFF. Meanwhile, a potential at an output terminal is pulled up toward a high potential side power supply VDD since a load TFT 903 operates in a saturated region at all times. On the other hand, when the input signal is an H signal (high potential side power supply VDD), the N-channel type TFT 904 is turned ON. The potential at the output node is pulled down toward the low potential side power supply GND if the current capacity of the n-channel type TFT 904 is set sufficiently larger than that of the load TFT 903.
However, there is the following problem in this case. FIG. 9C shows the waveform of the output from the TFT load-type inverter circuit. When the input signal is at L level, the potential at the output terminal is lower than VDD by an amount denoted by 907, namely by a threshold voltage of the load TFT 903 as shown in FIG. 9C. This is because few current flows in the load TFT 903 when the gate-source voltage of the load TFT 903 is smaller than the threshold voltage, thus the load TFT 903 is turned OFF. The source terminal of the load TFT 903 is an output terminal and the gate terminal thereof is connected to VDD here. Therefore, the potential at the output terminal is lower than the potential at the gate terminal by the threshold voltage. That is, the potential at the output terminal can be increased to be (VDD−VthN) at highest. Further, when the input signal is an H signal, the potential at the output terminal is higher than GND by an amount denoted by 908, depending on the ratio of the current capacities of the load TFT 903 to the n-channel type TFT 904. To bring the output potential sufficiently close to GND, it is necessary to sufficiently increase the current capacity of the n-channel type TFT 904 relatively to that of the load TFT 903.
That is, when using the above-described inverter circuit formed by using TFTs having only one conductivity, the amplitude of the output signal is attenuated relative to the amplitude of the input signal.
Hereupon, several methods for avoiding the problem that the amplitude of an output signal is attenuated have been studied (see Patent Documents 1 to 4 for example).
FIG. 33 shows a circuit diagram of an inverter circuit shown in Patent Documents 1 and 2. The circuit shown in FIG. 33 has the advantage that when the gate terminal of a transistor 3302 is brought into a floating state, a voltage at both terminals (potential difference between both terminals) of a capacitor 3304 does not change.
The operation of FIG. 33 is described next. A pair of signals inverted from each other is input to each of input terminals 3305 and 3306. First, an H signal (high potential side power supply VDD) is input to the input terminal 3306 and an L signal (low potential side power supply GND) is input to the input terminal 3305. Then, a transistor 3303 is turned ON and a potential at a terminal 3308 becomes equal to the potential of the L signal (low potential side power supply GND). Meanwhile, a transistor 3301 is turned ON as the potential at the input terminal 3305 is equal to the potential of the L signal (low potential side power supply GND). As a result, a terminal 3307 becomes equal to the potential of the L signal (low potential side power supply GND). That is, the voltage at both terminals (potential difference between both terminals) of the capacitor 3304 becomes equal to 0 V.
Next, when an H signal (high potential side power supply VDD) is input to the input terminal 3305 and an L signal (low potential side power supply GND) is input to the input terminal 3306, the transistor 3303 is turned OFF. Since the potential at the input terminal 3305 is equal to the potential of the H signal (high potential side power supply VDD), the transistor 3301 is turned ON and thus the potential at the terminal 3307 is increased. When the gate-source voltage of the transistor 3302 becomes higher than the threshold voltage, the transistor 3302 is turned ON and a potential at the terminal 3308 starts increasing. In such a case, when the potential at the terminal 3307 keeps on increasing, the transistor 3301 is turned OFF at the end. This is because, as the terminal 3307 corresponds to the source terminal of the transistor 3301, the gate-source voltage of the transistor 3301 becomes smaller when the potential at the terminal 3307 is increased, thus reaches the threshold voltage at the end. When the gate-source voltage of the transistor 3301 becomes equal to the threshold voltage, the transistor 3301 is turned OFF. Therefore, the current flow from the terminal 3305 to the terminal 3307 is cut off. That is, the terminal 3307 is brought into a floating state. As a result, the voltage at both terminals (potential difference between both terminals) of the capacitor 3304 does not change any more.
In the case where the potential at the terminal 3308 still keeps on increasing at the point when the transistor 3301 is turned OFF, the transistor 3302 is ON. That is, the gate-source voltage of the transistor 3302, namely the voltage at both terminals (potential difference between both terminals) of the capacitor 3304 is larger than the threshold voltage of the transistor 3302. Therefore, the potential at the terminal 3308 is further increased. At this time, the potential at the terminal 3307 is also increased. This is because, when the potential at either terminal of the capacitor 3304 (the terminal 3308) is increased, the potential at the other terminal (the terminal 3307) is also increased since the voltage at both terminals (potential difference between both terminals) of the capacitor 3304 does not change any more. Thus, the potential at the terminal 3308 keeps on increasing and reaches the high potential side power supply VDD at the end. While the potential at the terminal 3308 is increasing until it reaches the high potential side power supply VDD, the transistor 3302 is constantly ON. The capacitor 3304 holds the very voltage at which the transistor 3301 is turned OFF. Therefore, the potential at the terminal 3307 is higher than the high potential side power supply VDD by the voltage which is stored in the capacitor 3304.
That is, the potentials at the terminals 3307 and 3308 are equal to or higher than the high potential side power supply VDD. Thus, it can be prevented that the amplitude of the output signal becomes smaller than that of the input signal.
Such a circuit is generally referred to as a bootstrap circuit.
[Patent Document 1] Japanese Patent Laid-Open No. Hei 8-50790
[Patent Document 2] Japanese Patent No. 3330746 Specification
[Patent Document 3] Japanese Patent No. 3092506 Specification
[Patent Document 4] Japanese Patent Laid-Open No. 2002-328643